System-on-chip technology today facilitates provision of even rather complex systems for communication between different modules of an integrated circuit (for example, a processing unit, memories, peripherals, and other dedicated units) so as to ensure observance of the specifications of performance of the system.
Various applications foresee the use of first-in/first-out (FIFO) queues between devices with different clock frequencies. For example, a FIFO queue can be set between a first device, for example a microprocessor, which writes information in the FIFO queue and a second device, for example a peripheral or a second microprocessor, which reads the information from the FIFO queue. Each device reads and writes data in the FIFO queue with a rate equal to that of its own clock. However, FIFO queues can be used also in synchronous systems.
In complex digital systems, the possibility of carrying out a sort of “anticipation” by investigating the subsequent contents of a queue, an operation that is also known by the term “look-ahead”, can be particularly useful for anticipating execution of some processes or tasks and for implementing specific system functions. Currently, specific known approaches to address this problem are not available.
The inventors have noted that, in principle, an approach represented in FIG. 1 could be envisaged, in which, for search of a value, all the data stored in the FIFO queue are checked. In the communication between a master node 10 and a slave node 20 control information is exchanged on control lines 16. This occurs both in the case where the two nodes 10 and 20 use two different clocks and in the case where the two nodes use one and the same clock. The master node is responsible for “writing” or storing new data in a FIFO queue 30, getting them to travel on an input line 12, while the slave node 20 is responsible for “reading” or extracting the data stored in the queue 30 through an output line 14. The master node 10 thus works at a first end of the FIFO queue 30, while the slave node 20 works at the other end.
The presence of the FIFO queue 30 serves to enable co-existence of the two domains with different clock frequency. The FIFO queue 30 can be in particular a buffer used for regulating the flow of data in the communication between devices that work at different rates. It will on the other hand be appreciated that, in on-chip communication systems, the use of buffers is not necessarily linked to the need to regulate the flow of data between devices that work at different speeds. Other examples of possible use of buffers are: protocol conversion, packeting as in the case of network-on-chip, or conversion of data size.
The module designated in FIG. 1 by the reference number 25 represents the prediction, or look-ahead, unit. The approach here hypothesized envisages a parallel check of all the data stored in the FIFO queue 30. Each module contained in the unit 25, and designated by the reference number 40, is fundamentally a comparator module designed to compare the values present on its inputs 42, 44 with the purpose of selecting and issuing at output 46 the desired value (which can be a value sought, the maximum value, or the minimum value). The value selected by the comparator 40 is then made available at output and used as input for the next comparator 40 in the cascade, which compares it with a next element in the FIFO queue 30. At the end of all the comparisons, the value sought is made available by the unit 25 at output on the line 18.
This approach may prove, however, very slow and costly: in fact, for a queue of size N, N−1 comparators are used and there is a long critical path provided by the cascade of the comparators. Furthermore, this approach may prove far from flexible in so far as the length of the critical path and the production cost increase with the increase of the length of the queue.